/**
* @file        sdram_map_define.h
* @brief       None
* @note        None
* @attention   None
*
* <B><I>Copyright 2018 Socionext Inc.</I></B>
*/

#ifndef _SDRAM_MAP_DEFINE_H_
#define _SDRAM_MAP_DEFINE_H_

#define SDRAM_SIZ_CH0_TOP	(0x40000000)
#define SDRAM_ADR_CH0_TOP	(0x40000000)

#define SDRAM_SIZ_LINUX_WORK	(0x1000000)
#define SDRAM_ADR_LINUX_WORK	(0x40000000)

#define SDRAM_SIZ_LINUX_KERNEL	(0x2000000)
#define SDRAM_ADR_LINUX_KERNEL	(0x41000000)

#define SDRAM_SIZ_LINUX_INITRAMFS	(0x9700000)
#define SDRAM_ADR_LINUX_INITRAMFS	(0x43000000)

#define SDRAM_SIZ_LINUX_USER_FWUP	(0x3200000)
#define SDRAM_ADR_LINUX_USER_FWUP	(0x4C700000)

#define SDRAM_SIZ_LINUX_LOG	(0x500000)
#define SDRAM_ADR_LINUX_LOG	(0x4F900000)

#define SDRAM_SIZ_LINUX_RTOS_COMMON	(0x0)
#define SDRAM_ADR_LINUX_RTOS_COMMON	(0x4FE00000)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_IPCU_BUFFER	(0x90000)
#define SDRAM_ADR_LINUX_RTOS_COMMON_IPCU_BUFFER	(0x4FE00000)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_IPCU_SYNC	(0x48)
#define SDRAM_ADR_LINUX_RTOS_COMMON_IPCU_SYNC	(0x4FE90000)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_TS_READ_POINTER	(0x4)
#define SDRAM_ADR_LINUX_RTOS_COMMON_TS_READ_POINTER	(0x4FE90048)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_TS_WRITE_POINTER	(0x4)
#define SDRAM_ADR_LINUX_RTOS_COMMON_TS_WRITE_POINTER	(0x4FE9004C)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_STRING_AREA	(0x400)
#define SDRAM_ADR_LINUX_RTOS_COMMON_STRING_AREA	(0x4FE90050)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_TERMINAL_IO	(0x32014)
#define SDRAM_ADR_LINUX_RTOS_COMMON_TERMINAL_IO	(0x4FE90450)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_CAPABILITY_INFO	(0x3B6C)
#define SDRAM_ADR_LINUX_RTOS_COMMON_CAPABILITY_INFO	(0x4FEC2468)

#define SDRAM_SIZ_LINUX_RTOS_COMMON_MEMORY	(0xFFC00)
#define SDRAM_ADR_LINUX_RTOS_COMMON_MEMORY	(0x4FF00000)

#define SDRAM_SIZ_GR_IPCU_COMMAND	(0x300)
#define SDRAM_ADR_GR_IPCU_COMMAND	(0x4FFFFC00)

#define SDRAM_SIZ_LINUX_RESUME_MEMORY_SECOND_CPU	(0x10)
#define SDRAM_ADR_LINUX_RESUME_MEMORY_SECOND_CPU	(0x4FFFFF00)

#define SDRAM_SIZ_LINUX_RESUME_MEMORY_RESUME	(0x10)
#define SDRAM_ADR_LINUX_RESUME_MEMORY_RESUME	(0x4FFFFF10)

#define SDRAM_SIZ_RTOS_WARM_BOOT_ADDRESS	(0x4)
#define SDRAM_ADR_RTOS_WARM_BOOT_ADDRESS	(0x4FFFFF20)

#define SDRAM_SIZ_START_LINUX_RESUME	(0x4)
#define SDRAM_ADR_START_LINUX_RESUME	(0x4FFFFF24)

#define SDRAM_SIZ_LINUX_COMPLITE_SUSPEND	(0x4)
#define SDRAM_ADR_LINUX_COMPLITE_SUSPEND	(0x4FFFFF28)

#define SDRAM_SIZ_BOOT_LOADER	(0x70000)
#define SDRAM_ADR_BOOT_LOADER	(0x50000000)

#define SDRAM_SIZ_PARTITION TALBE	(0x10000)
#define SDRAM_ADR_PARTITION TALBE	(0x50070000)

#define SDRAM_SIZ_CM0_RTOS_COMMON	(0x4000)
#define SDRAM_ADR_CM0_RTOS_COMMON	(0x50080000)

#define SDRAM_SIZ_CH0_RTOS_IMAGE_WORK	(0x1E9FC140)
#define SDRAM_ADR_CH0_RTOS_IMAGE_WORK	(0x50084000)

#define SDRAM_SIZ_CH0_RTOS_MOVIE_WORK	(0x1157F2A0)
#define SDRAM_ADR_CH0_RTOS_MOVIE_WORK	(0x6EA80140)

#define SDRAM_SIZ_CH0_END	(0x0)
#define SDRAM_ADR_CH0_END	(0x80000000)

#define SDRAM_SIZ_CH1_TOP	(0x40000000)
#define SDRAM_ADR_CH1_TOP	(0xA0000000)

#define SDRAM_SIZ_RTOS_ROM	(0x2000000)
#define SDRAM_ADR_RTOS_ROM	(0xA0000000)

#define SDRAM_SIZ_RTOS_RAM	(0x4800000)
#define SDRAM_ADR_RTOS_RAM	(0xA2000000)

#define SDRAM_SIZ_MDF_HEAP_AREA	(0x100000)
#define SDRAM_ADR_MDF_HEAP_AREA	(0xA6800000)

#define SDRAM_SIZ_HOST_RESOURCE_DATA_AREA	(0xA00000)
#define SDRAM_ADR_HOST_RESOURCE_DATA_AREA	(0xA6900000)

#define SDRAM_SIZ_USER_SET_DATA_MAIN	(0x20000)
#define SDRAM_ADR_USER_SET_DATA_MAIN	(0xA7300000)

#define SDRAM_SIZ_USER_SET_DATA_WORK	(0x20000)
#define SDRAM_ADR_USER_SET_DATA_WORK	(0xA7320000)

#define SDRAM_SIZ_IQ_DATA_AREA	(0x100000)
#define SDRAM_ADR_IQ_DATA_AREA	(0xA7340000)

#define SDRAM_BNK_HOST_LCD_OSD_FRAME_DATA_AREA	(4)
#define SDRAM_SIZ_HOST_LCD_OSD_FRAME_DATA_AREA	(0x96000)
#define SDRAM_ADR_HOST_LCD_OSD_FRAME_DATA_AREA_0	(0xA7440000)
#define SDRAM_ADR_HOST_LCD_OSD_FRAME_DATA_AREA_1	(0xA74D6000)
#define SDRAM_ADR_HOST_LCD_OSD_FRAME_DATA_AREA_2	(0xA756C000)
#define SDRAM_ADR_HOST_LCD_OSD_FRAME_DATA_AREA_3	(0xA7602000)

#define SDRAM_BNK_HOST_HDMI_OSD_FRAME_DATA_AREA	(2)
#define SDRAM_SIZ_HOST_HDMI_OSD_FRAME_DATA_AREA	(0x3F4800)
#define SDRAM_ADR_HOST_HDMI_OSD_FRAME_DATA_AREA_0	(0xA7698000)
#define SDRAM_ADR_HOST_HDMI_OSD_FRAME_DATA_AREA_1	(0xA7A8C800)

#define SDRAM_SIZ_AUDIO_BUZZER_DATA_AREA	(0xF4240)
#define SDRAM_ADR_AUDIO_BUZZER_DATA_AREA	(0xA7E81000)

#define SDRAM_SIZ_HOST_WAV_READ_MEM_LOCATION_AREA	(0x927C0)
#define SDRAM_ADR_HOST_WAV_READ_MEM_LOCATION_AREA	(0xA7F75240)

#define SDRAM_BNK_AUDIO_CAPTURE_AREA	(2)
#define SDRAM_SIZ_AUDIO_CAPTURE_AREA	(0x68000)
#define SDRAM_ADR_AUDIO_CAPTURE_AREA_0	(0xA8007A00)
#define SDRAM_ADR_AUDIO_CAPTURE_AREA_1	(0xA806FA00)

#define SDRAM_BNK_AUDIO_CAPTURE_PLUGIN1_AREA	(2)
#define SDRAM_SIZ_AUDIO_CAPTURE_PLUGIN1_AREA	(0xBC000)
#define SDRAM_ADR_AUDIO_CAPTURE_PLUGIN1_AREA_0	(0xA80D7A00)
#define SDRAM_ADR_AUDIO_CAPTURE_PLUGIN1_AREA_1	(0xA8193A00)

#define SDRAM_SIZ_AUDIO_OUT_AREA	(0x60000)
#define SDRAM_ADR_AUDIO_OUT_AREA	(0xA824FA00)

#define SDRAM_BNK_LCD_MAIN	(3)
#define SDRAM_SIZ_LCD_MAIN	(0x70800)
#define SDRAM_ADR_LCD_MAIN_0	(0xA82AFA00)
#define SDRAM_ADR_LCD_MAIN_1	(0xA8320200)
#define SDRAM_ADR_LCD_MAIN_2	(0xA8390A00)

#define SDRAM_SIZ_HOST_LCD_OSD_FRAME_DATA_LOAD_AREA	(0x258000)
#define SDRAM_ADR_HOST_LCD_OSD_FRAME_DATA_LOAD_AREA	(0xA8402000)

#define SDRAM_SIZ_HOST_HDMI_OSD_FRAME_DATA_LOAD_AREA	(0x7E9000)
#define SDRAM_ADR_HOST_HDMI_OSD_FRAME_DATA_LOAD_AREA	(0xA865A000)

#define SDRAM_SIZ_DSP_AREA	(0x400000)
#define SDRAM_ADR_DSP_AREA	(0xA8E43000)

#define SDRAM_SIZ_FS_COPY_BUFFER_AREA	(0x100000)
#define SDRAM_ADR_FS_COPY_BUFFER_AREA	(0xA9243000)

#define SDRAM_SIZ_CH1_RTOS_IMAGE_WORK	(0x19EB9000)
#define SDRAM_ADR_CH1_RTOS_IMAGE_WORK	(0xA9343000)

#define SDRAM_SIZ_CH1_RTOS_MOVIE_WORK	(0x1CE04000)
#define SDRAM_ADR_CH1_RTOS_MOVIE_WORK	(0xC31FC000)

#define SDRAM_SIZ_CH1_END	(0x0)
#define SDRAM_ADR_CH1_END	(0xE0000000)

#define SDRAM_SIZ_COMMON_MEMORY	(0xFFC00)
#define SDRAM_ADR_COMMON_MEMORY	(0x4FF00000)

#define SDRAM_SIZ_COMMON_NUM	(0x17)
#define SDRAM_ADR_COMMON_NUM	(0x4FF00000)

#define SDRAM_SIZ_COMMON_0	(0x90000)
#define SDRAM_ADR_COMMON_0	(0x4FE00000)

#define SDRAM_SIZ_COMMON_1	(0x48)
#define SDRAM_ADR_COMMON_1	(0x4FE90000)

#define SDRAM_SIZ_COMMON_2	(0x4)
#define SDRAM_ADR_COMMON_2	(0x4FE90048)

#define SDRAM_SIZ_COMMON_3	(0x4)
#define SDRAM_ADR_COMMON_3	(0x4FE9004C)

#define SDRAM_SIZ_COMMON_4	(0x5880000)
#define SDRAM_ADR_COMMON_4	(0x6E5E0000)

#define SDRAM_SIZ_COMMON_5	(0x32014)
#define SDRAM_ADR_COMMON_5	(0x4FE90450)

#define SDRAM_SIZ_COMMON_6	(0x400)
#define SDRAM_ADR_COMMON_6	(0x4FE90050)

#define SDRAM_SIZ_COMMON_7	(0x2C80000)
#define SDRAM_ADR_COMMON_7	(0xD09A0000)

#define SDRAM_SIZ_COMMON_8	(0x304000)
#define SDRAM_ADR_COMMON_8	(0xC31FC000)

#define SDRAM_SIZ_COMMON_9	(0x0)
#define SDRAM_ADR_COMMON_9	(0x0)

#define SDRAM_SIZ_COMMON_10	(0x3330000)
#define SDRAM_ADR_COMMON_10	(0x7BDC8000)

#define SDRAM_SIZ_COMMON_11	(0x1E9FC140)
#define SDRAM_ADR_COMMON_11	(0x50084000)

#define SDRAM_SIZ_COMMON_12	(0x19EB9000)
#define SDRAM_ADR_COMMON_12	(0xA9343000)

#define SDRAM_SIZ_COMMON_13	(0x3B6C)
#define SDRAM_ADR_COMMON_13	(0x4FEC2468)

#define SDRAM_SIZ_COMMON_14	(0x0)
#define SDRAM_ADR_COMMON_14	(0x0)

#define SDRAM_SIZ_COMMON_15	(0x0)
#define SDRAM_ADR_COMMON_15	(0x0)

#define SDRAM_SIZ_COMMON_16	(0x0)
#define SDRAM_ADR_COMMON_16	(0x0)

#define SDRAM_SIZ_COMMON_17	(0x258000)
#define SDRAM_ADR_COMMON_17	(0xA8402000)

#define SDRAM_SIZ_COMMON_18	(0x7E9000)
#define SDRAM_ADR_COMMON_18	(0xA865A000)

#define SDRAM_SIZ_COMMON_19	(0x258000)
#define SDRAM_ADR_COMMON_19	(0x50084000)

#define SDRAM_SIZ_COMMON_20	(0x7E9000)
#define SDRAM_ADR_COMMON_20	(0x50084000)

#define SDRAM_SIZ_COMMON_21	(0x0)
#define SDRAM_ADR_COMMON_21	(0x0)

#define SDRAM_SIZ_COMMON_22	(0x0)
#define SDRAM_ADR_COMMON_22	(0x0)

#define SDRAM_SIZ_COMMON_23	(0x0)
#define SDRAM_ADR_COMMON_23	(0x0)

#define SDRAM_SIZ_COMMON_24	(0x0)
#define SDRAM_ADR_COMMON_24	(0x0)

#define SDRAM_SIZ_COMMON_25	(0x0)
#define SDRAM_ADR_COMMON_25	(0x0)

#define SDRAM_SIZ_COMMON_26	(0x0)
#define SDRAM_ADR_COMMON_26	(0x0)

#define SDRAM_SIZ_COMMON_27	(0x0)
#define SDRAM_ADR_COMMON_27	(0x0)

#define SDRAM_SIZ_COMMON_28	(0x0)
#define SDRAM_ADR_COMMON_28	(0x0)

#define SDRAM_SIZ_COMMON_29	(0x0)
#define SDRAM_ADR_COMMON_29	(0x0)

#define SDRAM_SIZ_COMMON_30	(0x0)
#define SDRAM_ADR_COMMON_30	(0x0)

#define SDRAM_SIZ_RESERVED	(0x0)
#define SDRAM_ADR_RESERVED	(0x0)


#endif
